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Std.Tactic.BVDecide.Bitblast.BVExpr.Circuit.Impl.Operations.Add

This module contains the implementation of a bitblaster for BitVec.add. The implemented circuit is a ripple carry adder.

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        @[simp]
        theorem Std.Tactic.BVDecide.BVExpr.bitblast.FullAdderInput.lhs_cast {α : Type} [Hashable α] [DecidableEq α] {aig1 aig2 : Sat.AIG α} (s : FullAdderInput aig1) (hcast : aig1.decls.size aig2.decls.size) :
        (s.cast hcast).lhs = s.lhs.cast hcast
        @[simp]
        theorem Std.Tactic.BVDecide.BVExpr.bitblast.FullAdderInput.rhs_cast {α : Type} [Hashable α] [DecidableEq α] {aig1 aig2 : Sat.AIG α} (s : FullAdderInput aig1) (hcast : aig1.decls.size aig2.decls.size) :
        (s.cast hcast).rhs = s.rhs.cast hcast
        @[simp]
        theorem Std.Tactic.BVDecide.BVExpr.bitblast.FullAdderInput.cin_cast {α : Type} [Hashable α] [DecidableEq α] {aig1 aig2 : Sat.AIG α} (s : FullAdderInput aig1) (hcast : aig1.decls.size aig2.decls.size) :
        (s.cast hcast).cin = s.cin.cast hcast
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                      @[irreducible]
                      def Std.Tactic.BVDecide.BVExpr.bitblast.blastAdd.go {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (lhs rhs : aig.RefVec w) (curr : Nat) (hcurr : curr w) (cin : aig.Ref) (s : aig.RefVec curr) :
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                          @[irreducible]
                          theorem Std.Tactic.BVDecide.BVExpr.bitblast.blastAdd.go_le_size {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (curr : Nat) (hcurr : curr w) (cin : aig.Ref) (s : aig.RefVec curr) (lhs rhs : aig.RefVec w) :
                          aig.decls.size (go aig lhs rhs curr hcurr cin s).aig.decls.size
                          @[irreducible]
                          theorem Std.Tactic.BVDecide.BVExpr.bitblast.blastAdd.go_decl_eq {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (curr : Nat) (hcurr : curr w) (cin : aig.Ref) (s : aig.RefVec curr) (lhs rhs : aig.RefVec w) (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < (go aig lhs rhs curr hcurr cin s).aig.decls.size) :
                          (go aig lhs rhs curr hcurr cin s).aig.decls[idx] = aig.decls[idx]